The Megahertz Myth became a promotional tactic due to differences between the PC's INTEL 8086 processor and Apple's Rockwell 6502 processor. The 8086 ran at 4.77MHz while the 6502 ran at 1MHz. However, instructions on the 6502 needed fewer cycles; so many fewer, in fact, that it ran faster than the 8086. Why do some instructions need fewer cycles? And why can't the instructions of the 6502, needing fewer cycles, be combined with a fast cycling processor of the 8086?
Wikipedia's article for instructions per cycle (IPC) says
Factors governing IPC
A given level of instructions per second can be achieved with a high IPC and a low clock speed...or from a low IPC and high clock speed.
Why can't you have both high instructions per cycle and high clock speed?
Maybe this has to do with what a clock cycle is? Wikipedia mentions synchronization of circuits? Not sure what that means.
Or maybe this has to do with how a pipeline works? I'm not sure why instructions in a short pipeline are different from instructions in a long pipeline.
Any insight would be great! Just trying to understand the architecture behind the myth. Thanks!
References:
Instruction per Cycle vs Increased Cycle Count
http://en.wikipedia.org/wiki/Instructions_per_cycle
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